1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells for data storage and a method of fabricating the same.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the data to be permanently stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
Most ROMs are identical in semiconductor structure except for the different data stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for the programming and then the semi-finished products can be stocked in inventory awaiting customer orders. The customer then furnishes the data to the factory where the data are to be stored into the semi-finished ROMs by using the so-called mask programming process. This procedure is now a standard method in the semiconductor industry for fabricating ROMs.
In most ROMs, metal-oxide semiconductor field-effect transistors (MOSFET) are used as the memory cells for data stored. In the mask programming stage, impurities are selectively diffused into specific channels in the MOSFET memory cells so as to change the threshold voltage thereof, thereby setting the MOSFET memory cells to ON/OFF states representing different binary data. The MOSFET memory cells are connected to the external circuits via a plurality of polysilicon-based word lines and bit lines. The channel regions are located beneath the word lines and between each pair of adjacent bit lines. Whether one MOSFET memory cell is set to store a binary digit of 0 or 1 is dependent on whether the associated channel is diffused with impurities or not. If the associated channel is diffused with impurities, the MOSFET memory cell is set to have a low threshold voltage, effectively setting the MOSFET memory cell to a permanently-ON state representing the storage of a binary digit of 0, for example; otherwise, the MOSFET memory cell is set to have a high threshold voltage, effectively setting the MOSFET memory cell to a permanently-OFF state representing the storage of a binary digit of 1.
Referring to FIG. 1, there is shown the circuit diagram of a conventional mask ROM device 10, which includes a plurality of crosswise-arranged parallel-spaced word lines [ WL0, WL1, WL2, WL3] and a plurality of lengthwise-arranged parallel-spaced bit lines [BL0, BL1, BL2, BL3, BL4]. Each segment of the word lines located between one neighboring pair of the bit lines is the location where one MOSFET memory cell is formed. The binary data stored in each MOSFET memory cell is dependent on the threshold voltage of the same. For instance, if one MOSFET memory cell is custom-made with a low threshold voltage, it means that this MOSFET memory cell is set to a permanently-ON state representing the permanent storage of a binary digit of 0, for example. Conversely, if the MOSFET memory cell is custom-made with a high threshold voltage, it means that this MOSFET memory cell is set to a permanently-OFF state representing the permanent storage of a binary digit of 1, for example. In FIG. 1, for example, those memory cells that are set to store a binary digit of 1 are indicated by the labeling of a black box between the source/drain electrodes, as indicated by the one labeled with the reference numeral 14. Conversely, those memory cells that are not labeled with a black box are set to store a binary digit of 0, as indicated by the one labeled with the reference numeral 12.
To read data from the ROM device, a specific potential is applied to the corresponding bit lines and word lines. For instance, to read data from the memory cell 12 (which has a low threshold voltage indicating the storage of the binary data of 0), a potential is applied to the gate of the memory cell 12 via the word line WL0 and the drain of the same via the bit line BL0. Since the memory cell 12 is custom-made with a low threshold voltage, the applied potential will turn ON the MOSFET memory cell, thus causing a change in the current flowing in the bit line BL0. By contrast, since the memory cell 14 is custom-made with a high threshold voltage, the applied potential will not cause a change in the current flowing in the corresponding bit line BL2. By detecting the current changes in the bit lines, the external circuitry can determine whether the data is 0 or 1.
Referring to FIG. 2, there is shown a top view of the layout of part of the conventional ROM device of FIG. 1. This ROM device is based on a P-type silicon substrate 20. Through ion implantation with an N-type impurity material at selected areas on the silicon substrate 20, a plurality of parallel-spaced buried bit lines 22, 26 and complementary bit lines 24, 28 are formed. The buried bit lines 22, 26 are connected to a voltage source V, while the complementary bit lines 24, 28 are connected to ground. The ROM device is further formed with a plurality of parallel-spaced word lines WL0, WL1 intercrossing the buried bit lines 22, 26 and complementary bit lines 24, 28 substantially at right angles. This forms a plurality of MOSFET memory cells 30 (as indicated by the dashed boxes in FIG. 2) which have a low threshold voltage, and a plurality of MOSFET memory cells 32 which have a high threshold voltage.
Referring to FIG. 3, there is shown a schematic sectional diagram of a part of the ROM device of FIG. 2. This sectional diagram is used in particular to depict the programming of data into the ROM device. First, a silicon substrate 15 is prepared. Then, an N-type impurity material, such as arsenic (As), is diffused by means of ion implantation into selected regions of the silicon substrate 15 to form a plurality of parallel and substantially equally spaced N.sup.+ diffusion regions 11 serving as a plurality of bit lines. One channel region 16 is formed between each neighboring pair of the N.sup.+ diffusion regions (bit lines) 11. Subsequently, a thermal oxidation process is conducted on the wafer. Due to different oxidation rates at different regions, a thick oxidation layer 17a (which serves as an isolation layer) is formed over the N.sup.+ diffusion regions (bit lines) 11, while a thin oxidation layer 17b is formed over each channel region 16. After that, a plurality of parallel-spaced polysilicon layers 13 (which serve as word lines) are formed over the wafer in such as manner as to intercross the underlying N.sup.+ diffusion regions (bit lines) 11 substantially at right angles (only one of the polysilicon layers 13 is visible in the sectional diagram of FIG. 3 ). This completes the semi-finished product of the ROM device.
In the mask programming process, a mask 19 covers the top surface of the semi-finished product of the ROM device. This mask 19 is predefined to form a plurality of openings to expose those channel regions that are associated with the MOSFET memory cells that are to be set to a permanently-ON state. A P-type impurity material, such as boron, is diffused by ion implantation through the openings in the mask 19 into the corresponding channel regions. This completes the so-called code implant process.
In the finished product of the ROM device, the doped channels cause the associated MOSFET memory cells to have a low threshold voltage, thus setting them to a permanently-ON state representing the storage of a binary digit of 0. On the other hand, the undoped channels cause the associated MOSFET memory cells to have a high threshold voltage, thus setting them to a permanently-OFF state representing the storage of a binary digit of 1.
The foregoing ROM device, however, has the following two drawbacks. First, when the ROM device is further miniaturized, the application of a high concentration of impurities to selected channel regions could cause the undesired phenomena of lateral diffusion, junction leakage, and reduced breakdown voltage. This is due to the fact that the buried bit lines in the conventional ROM device are formed by implanting impurities into the silicon substrate. Second, since the process for fabricating the conventional ROM device involves the use of thermal oxidation to form the isolating oxidation layers, the planarization of the wafer surface is not very satisfactory. Poor planarization adversely affects the performance of the ROM device.